1. FIELD OF THE INVENTION
This invention pertains to packaging for power semiconductor devices generally, and specifically to hermetic packaging using a minimum number of interfaces between a semiconductor device and a heat sink.
2. DESCRIPTION OF THE RELATED ART
As electronic devices continue the trend towards more complexity and greater capability combined into an ever shrinking package, new ways are continually sought to package the devices. In the early days of electronics, vacuum tubes performed a variety of functions from amplification of electrical signals to switching and regulation of power supplies used to run motors, radios and other devices. With the advent of the transistor, semiconductor devices made from materials such as silicon, germanium, gallium-arsenide and other similar materials have gradually replaced the vacuum tube while simultaneously creating new applications. The reduction in power required to operate the transistor led to much more compact packaging since less thermal energy had to be dissipated from the package.
The advent of high power semiconductors has led to the nearly complete replacement of vacuum tubes by transistors. In the process, applications where many kilowatts of power are to be controlled may be managed by these semiconductors. Further, where high level integration must be achieved by use of a circuit board highly populated with closely spaced semiconductor devices, a large amount of thermal energy per unit area must be dissipated. These demands for greater integration in smaller packages and greater power handling capabilities in the same package size, all with equal or improved reliability, continue to drive developments in improved packaging.
In the prior art, the need for greater power dissipation is usually addressed through the use of metallic devices having large surface area, commonly referred to in the art as heat sinks. Various arrangements of fins and surface contours are commonly provided to increase the total surface area from which heat may be conducted, radiated, or otherwise removed. The material chosen is typically aluminum, due to good thermal conductivity combined with environmental stability. Attachment of the semiconductor device to a metallic heat sink may not be achieved through direct coupling since aluminum and other metals are electrically conductive and the heat sink would act to short circuit the device. Primarily because metals generally have better thermal conductivity than other materials, much opportunity for widely varying design has been created by the need for an electrical insulator between the semiconductor device and a metal heat sink.
Several methods aimed at improving thermal dissipation involve providing a thin dielectric layer between the semiconductor device and a metal heat sink. This has been the traditional approach at high power packaging for transistors, beginning shortly after the advent of the bipolar transistor. One popular package design is illustrated in U.S. Pat. No. 3,585,272. In that patent, a semiconductor device is mounted to an alumina substrate via a multi-layer bonding process wherein molybdenum, with a thermal expansion coefficient matching the silicon chip, is used to bond directly to the chip. Under the molybdenum layer is a heat dissipating copper slug which in turn is solder bonded to a gold film formed on the surface of the alumina substrate. The alumina is then thermally attached to an aluminum heat sink via "pliable, soft, high heat conductivity material." Silicone heat conductive grease is given as an example of one such material. In this patent, there are six layers between the device and the heat sink, including molybdenum, copper, solder, gold, alumina, and thermal grease. Clearly, the application of six different layers can lead to a multitude of problems that adversely affect the thermal performance of the package and add substantially to the manufactured cost of the device.
A similar concept is illustrated in U.S. Pat. No. 3,769,560 wherein a device is bonded to a beryllia substrate that is then attached to a large copper heat sink. U.S. Pat. No. 3,735,213 discloses a package having a glass or glass-ceramic substrate with a Kovar frame. In this package very poor thermal conductivity will occur between a mounted device and the exterior, owing to the poor thermal conductivity of glasses and glass-ceramics and the lack of heat sink. U.S. Pat. No. 4,227,036 discloses a copper heat sink laminated on one side with molybdenum and opposite the molybdenum, a ceramic substrate upon which components are presumably mounted. Upon the ceramic substrate is a ceramic side wall, and a Kovar or ceramic cap to close the package after wire bonding. The molybdenum under layer is required to compensate for the differing coefficients of thermal expansion between the copper and ceramic that would otherwise result in bowing of the substrate.
More recently, work has progressed on ceramic heat sink members not requiring the usual insulator interspersed between the semiconductor and the heat sink. U.S. Pat. No. 4,791,075 illustrates a ceramic substrate, described as being fabricated from silicon carbide, alumina, or aluminum nitride having through holes exterior to the hermetic device region, with lead-throughs passing out of the hermetic zone underneath a cap of ceramic or metal. U.S. Pat. No. 4,987,478 illustrates a device bonded to an aluminum nitride heat sink having interconnects directly bonded to the device that extend through a similar substrate to a package exterior.